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Machine Learning

Compact configurations improve hardware generation in one SECDED task

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#cost-performance#compact-configuration#correctness-gating

En termes simples

The paper introduces a way to make language models generate hardware designs. Instead of asking a model to write every line of a long hardware description, it can output a short list of settings, which a deterministic program expands into the design.

For one error-correcting memory-wrapper task, a model using the short configuration produced more designs that matched the reference than the same model writing code directly. The result applies to this bounded task, not hardware generation in general.

La recherche

For a 512-bit error-correcting memory, flat Verilog takes about 44,237 tokens, while an eight-field configuration takes 69. Can a model specify the design briefly and let a deterministic generator produce the full hardware description?

The method has a language model emit a short hardware configuration for a deterministic generator, then tests whether that representation improves correctness and feasibility.

The authors test whether changing what a model outputs can help with a task where a full hardware description is extremely long. Their method has the model provide a short configuration, which a deterministic generator expands into RTL.

With the same few-shot model and recipe, the configuration matched the reference more often than three code-like forms. This supports a representation advantage on the tested SECDED task, where correctness could be checked against a reference generator.

The evidence comes from one SECDED memory-wrapper task and generator. The small model that used the least GPU energy per correct design also silently changed 41% of tested illegal specifications into legal ones, and the out-of-distribution results had one run per regime.

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Détails

Article originalLearn the Interface, Not the Implementation: Output Representation Dominates Training Regime in LLM-Based RTL GenerationOuvrir l’original
Soumis à arXiv
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