A shared-memory race measures latency without a clock
PhotoFinish: Portable Timerless Probing of Microarchitectural Latencies · arXiv:2611.09879
In plain words
A computer’s cache and other internal parts can make the same operation take different amounts of time. PhotoFinish is a method that lets software notice some of those differences without using a clock.
Two threads race to finish different operations and write different values to the same shared spot. The last value reveals which operation took longer.
Across tested CPUs, adding a calibrated delay let the method distinguish a fast cache access from a slow memory access on every tested platform configuration.
The research
Small timing differences can reveal activity inside a computer, even when software cannot read a clock.
A way to compare operation delays directly could change what timer restrictions accomplish: in these tests, a shared-memory race still distinguished cache states across varied processors, including in a browser setting.
PhotoFinish compares two parallel operation paths through their final shared-memory writes to reveal which took longer, without reading a clock.
In native tests, the method classified cache states by racing a target memory access against a fixed reference on separate physical cores. Without padding, it reached an F1 score of at least 0.97 on 41 of 45 configurations; F1 combines how often accesses predicted to be fast really are fast with how many actual fast accesses are found.
With calibrated delay, all 45 configurations had a nonempty range of padding values where F1 exceeded 0.98, showing that shifting the race boundary can cover cases the unpadded race misses.
A comparison with counting-thread timers on the same cross-core configurations found similar or broader classification coverage for PhotoFinish. The evidence supports clock-free cache probing across the tested platforms, with padding extending its reach when calibration is available.
PhotoFinish reports which path finished later, not elapsed time. It requires concurrent threads and writable shared memory; padding also needs calibration, and distinguishing several states can take multiple measurements.
What the evidence shows
- A clock-free comparison
PhotoFinish is a timerless probing method for revealing microarchitectural latency differences, which can expose hidden machine state. It compares two parallel operation paths through their final writes to shared memory.
The question is whether that comparison can work across different processors without relying on a clock or a specialized processor feature.
- Padding extends coverage
For L1-hit versus DRAM-access classification on separate physical cores, calibrated padding extends PhotoFinish’s coverage across the native configurations. F1 combines how often accesses predicted to be fast really are fast with how many actual fast accesses are found.
The padded and unpadded results use different F1 criteria, so this shows broader coverage under the padded criterion, not a like-for-like score improvement.
- A timer fallback comparison
On the same 40 cross-core configurations, PhotoFinish and a counting-thread timer had similar coverage for classifying L1 hits versus DRAM accesses and last-level-cache hits versus DRAM accesses.
Padding increased PhotoFinish’s coverage on these tasks, but requires calibration; the comparison does not cover all native configurations.
- Evidence beyond native tests
The method also classified cache states in a browser test using WebAssembly, Web Workers and shared memory. A separate experiment used repeated measurements to infer last-level-cache slices on one Intel processor.
Together, these tests extend the evidence beyond native cache classification, while remaining tied to the specific browser setup and processor tested.
Deep
- Original paper authors
- Tristan Hornetz, Eduard Ebert, Lorenz Hetterich, Lukas Gerlach, Michael Schwarz
- Submitted to arXiv
- License
- Not specified by source